Developed a VHDL-based memory game for FPGA boards.
Implemented LED display of sequential patterns for player interaction. Integrated user input
via buttons for pattern repetition.
Developed comprehensive VHDL testbenches to simulate and verify the functionality of individual modules, including registers, counters, and display drivers.
Skills Developed
VHDL
Quartus
Simulation
Digital Logic
FPGA - Digital Clock
Designed and implemented a digital clock on an FPGA development board using VHDL.
Developed accurate timekeeping mechanism using a clock divider to generate a precise 1 Hz signal from the FPGA clock.
Implemented separate VHDL counter modules for seconds, minutes, and hours, ensuring proper overflow and reset at 60 seconds, 60 minutes, and 24.
